Principal Physical Design Engineer - Remote Opportunity

About the Role

We are seeking a Principal Physical Design Engineer to join our team at Astera Labs. This remote opportunity allows you to leverage your expertise in physical design while collaborating with a dynamic team focused on AI infrastructure solutions. As a Principal Physical Design Engineer, you will play a pivotal role in the design and execution of connectivity ASICs used by leading cloud service providers and OEMs.

What You'll Do

• Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems.
• Identify RTL issues early and collaborate with the frontend team on resolutions.
• Utilize hands-on experience with various custom clocking techniques.
• Work on high-speed designs with SERDES and DDR IPs.
• Understand PnR tool and signoff flows including Extraction, STA, Formality, EM-IR, and DRC/LVS.
• Manage ECO flow using PT DMSA and hyperscale models for larger chips.
• Define and manage I/O timing budgets across hierarchical designs.
• Partner closely with design, implementation, and verification teams to drive block/top convergence.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Science; Master’s preferred.
• At least 10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in PnR, Extraction, Timing closure, EM-IR, Formality, and DRC/LVS at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability in Tcl, Python, or Perl.
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Nice to Have

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• Familiarity with SystemVerilog/Verilog.

What We Offer

• Competitive salary range of $207,000 to $230,000 per year.
• Opportunity to work with cutting-edge AI infrastructure technologies.
• Collaborative and innovative work environment.
• Diverse and inclusive workplace culture.
• Remote work flexibility.