About the Role
We are seeking a talented Mid-Senior FPGA Developer to join our team at Fairwinds Technologies. This role focuses on developing high-performance, low-latency digital signal processing pipelines for adaptive Software Defined Radio (SDR) and Electronic Warfare (EW) systems. As an FPGA Developer, you will work with Xilinx/AMD RFSoC and Versal platforms, contributing to innovative projects that support U.S. Army and Department of Defense mission priorities.
What You'll Do
- Design and implement FPGA data paths for high-speed ADC/DAC streaming and DSP chains.
- Develop DDR-based capture and replay subsystems for EW and channel emulation.
- Integrate RF data converters, hardened DSP IP, and high-speed I/O interfaces.
- Support multi-band and multi-antenna SDR architectures.
- Participate in verification, integration, and hardware/software partitioning.
Requirements
- Bachelor’s or Master’s degree in Electrical or Computer Engineering.
- Proficiency in Verilog/SystemVerilog or VHDL and Vivado/Vitis toolchains.
- Experience with Xilinx/AMD RFSoC or Versal platforms.
- Must possess, or be eligible to obtain, an active DoD / DoW Secret Security Clearance.
Nice to Have
- Experience in adaptive communications and electronic warfare systems.
- Familiarity with satellite communication systems.
- Knowledge of AI/ML applications in signal processing.
What We Offer
- Competitive compensation package.
- Paid time off and retirement plans.
- Flexible work arrangements and relocation assistance.
- Opportunities for career growth and technical development.
- A collaborative engineering culture that values innovation and technical rigor.
This Mid-Senior FPGA Developer role offers a unique opportunity to work on cutting-edge technology in a collaborative environment. Enjoy competitive compensation and the chance to make a significant impact in defense and space manufacturing.
Who Will Succeed Here
Strong proficiency in Verilog and SystemVerilog for designing and implementing FPGA architectures, with hands-on experience using Xilinx/AMD tools such as Vivado and Vitis to optimize performance for DSP applications.
A self-motivated and adaptable problem solver, capable of working both independently and collaboratively in a hybrid work environment, effectively managing time and priorities to meet project deadlines.
Experience in developing and testing low-latency digital signal processing algorithms for SDR and EW systems, with a mindset geared towards continuous learning and improvement in emerging FPGA technologies.
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