Talantix.io
Astera Labs•05.03.26
AI SCORE 8.5

Senior Physical Design Chip Top Expert - Remote

$180K–$220K/year
RemoteSemiconductor Technology
Electrical Engineering•Chip Design•EDA Tools•Power Analysis•Signal Integrity

About the Role

Astera Labs is seeking a Senior Physical Design Chip Top Expert to join our innovative team remotely. This role is pivotal in leading chip-level physical design execution, focusing on the development of semiconductor chips that address critical data bottlenecks for AI scalability.

What You'll Do

  • Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity, and Timing/Physical signoff.
  • Oversee the chip convergence and ensure all PD disciplines meet the stringent signoff criteria.
  • Collaborate closely with Architecture, Design, DFT, and Product teams to optimize Power Performance Area (PPA).
  • Conduct feasibility studies for new architectures and optimize runs to achieve the best Quality of Results (QoR).
  • Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon.
  • Work closely with the Package team on Bump map to Ballout, ensuring all signal integrity aspects are considered.

Requirements

  • B.Sc. or M.Sc. in Electrical Engineering.
  • 15+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies.
  • Proven leadership experience with a "can-do" approach and excellent communication skills.
  • Deep expertise in Chip Top Level activities and signoff, RTL2GDS flows, including P&R, STA, Physical verification (DRC/LVS), and low-power implementation.
  • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus).

Nice to Have

  • Deep understanding of Power & Noise analysis (EM/IR).
  • Experience with DFT (Design for Test) integration.
  • Background in high-speed interfaces or data center protocols.

What We Offer

  • Competitive salary ranging from $180,000 to $220,000 annually.
  • Flexible remote work environment.
  • Opportunity to work on cutting-edge semiconductor technologies.
  • Collaborative and inclusive company culture that values diverse ideas and backgrounds.
  • Professional development opportunities and support for continuous learning.
Why This Job8.5 of 10

Astera Labs offers a unique opportunity for a Senior Physical Design Chip Top Expert to lead innovative chip development in a remote setting, with a competitive salary and a focus on diversity.

Salary Range
Required
0/1
Optional
0/1
Bonus
0/1

Who Will Succeed Here

→

In-depth expertise in EDA tools such as Cadence, Synopsys, and Mentor Graphics, enabling the candidate to efficiently manage complex chip designs and optimize physical design flows.

→

Strong analytical mindset with a focus on power analysis and signal integrity, ensuring robust performance and reliability of semiconductor chips in high-density environments.

→

Proven experience in leading remote teams effectively, demonstrating self-motivation and discipline while collaborating with cross-functional teams in a virtual setting.

Learning Resources

→Introduction to Physical Designcourse
→Understanding Chip Design: A Guide for Beginnersarticle
→Power Integrity Analysis for Integrated Circuitscourse

Career Path

Senior Physical Design Chip Top Expert(Now)→Technical Lead in Chip Design(1-2 years)→Director of Physical Design Engineering(3-5 years)

Market Overview

Market Size 2024
$24B
Annual Growth
8.5%
AI Adoption in Chip Design
45%
Investment in EDA Tools
+20%
Labour Demand for Chip Design Engineers
+15%
Avg Salary for Senior Chip Design Engineers
$150K

Skills & Requirements

Required
Electrical EngineeringChip DesignEDA Tools
Growing in Demand
Machine Learning for Chip Design3D IC DesignAdvanced Power Management Techniques
Declining
SPICE SimulationTraditional CMOS Design Techniques

Domain Trends

Increased Focus on Power Efficiency
With the rise of mobile and IoT devices, power efficiency is becoming critical. 70% of companies are prioritizing low-power designs to meet energy efficiency standards.
Adoption of AI in Design Automation
AI tools are increasingly being used for design automation, with 45% of companies reporting improved efficiency in the design process due to AI integration.
Shift to 3D Packaging
3D IC packaging is gaining traction, with a projected market growth rate of 12% annually as companies seek to enhance performance and reduce footprint.

Industry News

Loading latest industry news...

Finding relevant articles from the last 6 months

All job postings are automatically gathered by algorithms. We do not review or verify listings, be careful when applying and do not sign-in with iCloud or Google services.